715 lines
19 KiB
C
715 lines
19 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-19 SummerGift first version
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* 2018-12-25 zylx fix some bugs
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* 2019-06-10 SummerGift optimize PHY state detection process
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* 2019-09-03 xiaofan optimize link change detection process
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*/
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#include <board.h>
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#ifdef BSP_USING_ETH
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#include "drv_config.h"
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#include "drv_eth.h"
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#include <netif/ethernetif.h>
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#include <lwipopts.h>
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/*
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* Emac driver uses CubeMX tool to generate emac and phy's configuration,
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* the configuration files can be found in CubeMX_Config folder.
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*/
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/* debug option */
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//#define ETH_RX_DUMP
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//#define ETH_TX_DUMP
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//#define DRV_DEBUG
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#define LOG_TAG "drv.emac"
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#include <drv_log.h>
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#define MAX_ADDR_LEN 6
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struct rt_stm32_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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#ifndef PHY_USING_INTERRUPT_MODE
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rt_timer_t poll_link_timer;
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#endif
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/* interface address info, hw address */
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rt_uint8_t dev_addr[MAX_ADDR_LEN];
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/* ETH_Speed */
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rt_uint32_t ETH_Speed;
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/* ETH_Duplex_Mode */
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rt_uint32_t ETH_Mode;
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};
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static ETH_DMADescTypeDef *DMARxDscrTab, *DMATxDscrTab;
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static rt_uint8_t *Rx_Buff, *Tx_Buff;
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static ETH_HandleTypeDef EthHandle;
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static struct rt_stm32_eth stm32_eth_device;
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#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
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#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
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static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
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{
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unsigned char *buf = (unsigned char *)ptr;
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int i, j;
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for (i = 0; i < buflen; i += 16)
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{
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rt_kprintf("%08X: ", i);
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for (j = 0; j < 16; j++)
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if (i + j < buflen)
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rt_kprintf("%02X ", buf[i + j]);
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else
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rt_kprintf(" ");
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rt_kprintf(" ");
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for (j = 0; j < 16; j++)
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if (i + j < buflen)
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rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
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rt_kprintf("\n");
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}
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}
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#endif
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extern void phy_reset(void);
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/* EMAC initialization function */
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static rt_err_t rt_stm32_eth_init(rt_device_t dev)
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{
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__HAL_RCC_ETH_CLK_ENABLE();
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phy_reset();
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/* ETHERNET Configuration */
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EthHandle.Instance = ETH;
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EthHandle.Init.MACAddr = (rt_uint8_t *)&stm32_eth_device.dev_addr[0];
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EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE;
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EthHandle.Init.Speed = ETH_SPEED_100M;
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EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
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EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
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EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
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#ifdef RT_LWIP_USING_HW_CHECKSUM
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EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
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#else
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EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
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#endif
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HAL_ETH_DeInit(&EthHandle);
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/* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
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if (HAL_ETH_Init(&EthHandle) != HAL_OK)
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{
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LOG_E("eth hardware init failed");
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}
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else
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{
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LOG_D("eth hardware init success");
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}
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/* Initialize Tx Descriptors list: Chain Mode */
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HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, Tx_Buff, ETH_TXBUFNB);
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/* Initialize Rx Descriptors list: Chain Mode */
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HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, Rx_Buff, ETH_RXBUFNB);
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/* ETH interrupt Init */
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HAL_NVIC_SetPriority(ETH_IRQn, 0x07, 0);
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HAL_NVIC_EnableIRQ(ETH_IRQn);
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/* Enable MAC and DMA transmission and reception */
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if (HAL_ETH_Start(&EthHandle) == HAL_OK)
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{
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LOG_D("emac hardware start");
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}
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else
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{
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LOG_E("emac hardware start faild");
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return -RT_ERROR;
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}
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return RT_EOK;
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}
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static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
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{
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LOG_D("emac open");
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return RT_EOK;
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}
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static rt_err_t rt_stm32_eth_close(rt_device_t dev)
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{
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LOG_D("emac close");
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return RT_EOK;
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}
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static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
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{
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LOG_D("emac read");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
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{
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LOG_D("emac write");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
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{
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switch (cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if (args)
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{
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SMEMCPY(args, stm32_eth_device.dev_addr, 6);
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}
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else
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{
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return -RT_ERROR;
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}
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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/* ethernet device interface */
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/* transmit data*/
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rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
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{
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rt_err_t ret = RT_ERROR;
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HAL_StatusTypeDef state;
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struct pbuf *q;
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uint8_t *buffer = (uint8_t *)(EthHandle.TxDesc->Buffer1Addr);
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__IO ETH_DMADescTypeDef *DmaTxDesc;
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uint32_t framelength = 0;
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uint32_t bufferoffset = 0;
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uint32_t byteslefttocopy = 0;
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uint32_t payloadoffset = 0;
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DmaTxDesc = EthHandle.TxDesc;
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bufferoffset = 0;
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/* copy frame from pbufs to driver buffers */
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for (q = p; q != NULL; q = q->next)
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{
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/* Is this buffer available? If not, goto error */
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if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
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{
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LOG_D("buffer not valid");
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ret = ERR_USE;
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goto error;
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}
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/* Get bytes in current lwIP buffer */
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byteslefttocopy = q->len;
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payloadoffset = 0;
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/* Check if the length of data to copy is bigger than Tx buffer size*/
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while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE)
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{
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/* Copy data to Tx buffer*/
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SMEMCPY((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
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/* Point to next descriptor */
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DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
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/* Check if the buffer is available */
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if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
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{
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LOG_E("dma tx desc buffer is not valid");
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ret = ERR_USE;
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goto error;
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}
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buffer = (uint8_t *)(DmaTxDesc->Buffer1Addr);
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byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
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payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
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framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
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bufferoffset = 0;
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}
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/* Copy the remaining bytes */
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SMEMCPY((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
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bufferoffset = bufferoffset + byteslefttocopy;
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framelength = framelength + byteslefttocopy;
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}
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#ifdef ETH_TX_DUMP
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dump_hex(buffer, p->tot_len);
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#endif
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/* Prepare transmit descriptors to give to DMA */
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/* TODO Optimize data send speed*/
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LOG_D("transmit frame length :%d", framelength);
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/* wait for unlocked */
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while (EthHandle.Lock == HAL_LOCKED);
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state = HAL_ETH_TransmitFrame(&EthHandle, framelength);
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if (state != HAL_OK)
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{
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LOG_E("eth transmit frame faild: %d", state);
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}
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ret = ERR_OK;
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error:
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/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
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if ((EthHandle.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET)
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{
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/* Clear TUS ETHERNET DMA flag */
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EthHandle.Instance->DMASR = ETH_DMASR_TUS;
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/* Resume DMA transmission*/
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EthHandle.Instance->DMATPDR = 0;
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}
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return ret;
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}
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/* receive data*/
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struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
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{
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struct pbuf *p = NULL;
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struct pbuf *q = NULL;
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HAL_StatusTypeDef state;
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uint16_t len = 0;
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uint8_t *buffer;
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__IO ETH_DMADescTypeDef *dmarxdesc;
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uint32_t bufferoffset = 0;
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uint32_t payloadoffset = 0;
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uint32_t byteslefttocopy = 0;
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uint32_t i = 0;
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/* Get received frame */
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state = HAL_ETH_GetReceivedFrame_IT(&EthHandle);
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if (state != HAL_OK)
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{
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LOG_D("receive frame faild");
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return NULL;
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}
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/* Obtain the size of the packet and put it into the "len" variable. */
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len = EthHandle.RxFrameInfos.length;
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buffer = (uint8_t *)EthHandle.RxFrameInfos.buffer;
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LOG_D("receive frame len : %d", len);
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if (len > 0)
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{
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/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
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p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
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}
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#ifdef ETH_RX_DUMP
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dump_hex(buffer, p->tot_len);
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#endif
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if (p != NULL)
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{
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dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
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bufferoffset = 0;
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for (q = p; q != NULL; q = q->next)
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{
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byteslefttocopy = q->len;
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payloadoffset = 0;
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/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
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while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE)
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{
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/* Copy data to pbuf */
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SMEMCPY((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
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/* Point to next descriptor */
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dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
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buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
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byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
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payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
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bufferoffset = 0;
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}
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/* Copy remaining data in pbuf */
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SMEMCPY((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
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bufferoffset = bufferoffset + byteslefttocopy;
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}
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}
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/* Release descriptors to DMA */
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/* Point to first descriptor */
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dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
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/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
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for (i = 0; i < EthHandle.RxFrameInfos.SegCount; i++)
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{
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dmarxdesc->Status |= ETH_DMARXDESC_OWN;
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dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
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}
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/* Clear Segment_Count */
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EthHandle.RxFrameInfos.SegCount = 0;
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/* When Rx Buffer unavailable flag is set: clear it and resume reception */
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if ((EthHandle.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
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{
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/* Clear RBUS ETHERNET DMA flag */
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EthHandle.Instance->DMASR = ETH_DMASR_RBUS;
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/* Resume DMA reception */
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EthHandle.Instance->DMARPDR = 0;
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}
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return p;
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}
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/* interrupt service routine */
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void ETH_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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HAL_ETH_IRQHandler(&EthHandle);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
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{
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rt_err_t result;
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result = eth_device_ready(&(stm32_eth_device.parent));
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if (result != RT_EOK)
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{
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LOG_I("RxCpltCallback err = %d", result);
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}
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}
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void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
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{
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LOG_E("eth err");
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}
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enum {
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PHY_LINK = (1 << 0),
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PHY_100M = (1 << 1),
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PHY_FULL_DUPLEX = (1 << 2),
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};
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static void phy_linkchange()
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{
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static rt_uint8_t phy_speed = 0;
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rt_uint8_t phy_speed_new = 0;
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rt_uint32_t status;
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HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
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LOG_D("phy basic status reg is 0x%X", status);
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if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
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{
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rt_uint32_t SR = 0;
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phy_speed_new |= PHY_LINK;
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HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR);
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LOG_D("phy control status reg is 0x%X", SR);
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if (PHY_Status_SPEED_100M(SR))
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{
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phy_speed_new |= PHY_100M;
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}
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if (PHY_Status_FULL_DUPLEX(SR))
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{
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phy_speed_new |= PHY_FULL_DUPLEX;
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}
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}
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if (phy_speed != phy_speed_new)
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{
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phy_speed = phy_speed_new;
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if (phy_speed & PHY_LINK)
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{
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LOG_D("link up");
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if (phy_speed & PHY_100M)
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{
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LOG_D("100Mbps");
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stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
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}
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else
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{
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stm32_eth_device.ETH_Speed = ETH_SPEED_10M;
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LOG_D("10Mbps");
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}
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if (phy_speed & PHY_FULL_DUPLEX)
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{
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LOG_D("full-duplex");
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stm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
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}
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else
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{
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LOG_D("half-duplex");
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stm32_eth_device.ETH_Mode = ETH_MODE_HALFDUPLEX;
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}
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/* send link up. */
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eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
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}
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else
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{
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LOG_I("link down");
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eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
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}
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}
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}
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#ifdef PHY_USING_INTERRUPT_MODE
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static void eth_phy_isr(void *args)
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{
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rt_uint32_t status = 0;
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HAL_ETH_ReadPHYRegister(&EthHandle, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
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LOG_D("phy interrupt status reg is 0x%X", status);
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phy_linkchange();
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}
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#endif /* PHY_USING_INTERRUPT_MODE */
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static void phy_monitor_thread_entry(void *parameter)
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{
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uint8_t phy_addr = 0xFF;
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uint8_t detected_count = 0;
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while(phy_addr == 0xFF)
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{
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/* phy search */
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rt_uint32_t i, temp;
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for (i = 0; i <= 0x1F; i++)
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{
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EthHandle.Init.PhyAddress = i;
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HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ID1_REG, (uint32_t *)&temp);
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if (temp != 0xFFFF && temp != 0x00)
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{
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phy_addr = i;
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break;
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}
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}
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detected_count++;
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rt_thread_mdelay(1000);
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if (detected_count > 10)
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{
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LOG_E("No PHY device was detected, please check hardware!");
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}
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}
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LOG_D("Found a phy, address:0x%02X", phy_addr);
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/* RESET PHY */
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LOG_D("RESET PHY!");
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HAL_ETH_WritePHYRegister(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK);
|
|
rt_thread_mdelay(2000);
|
|
HAL_ETH_WritePHYRegister(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK);
|
|
|
|
phy_linkchange();
|
|
#ifdef PHY_USING_INTERRUPT_MODE
|
|
/* configuration intterrupt pin */
|
|
rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
|
|
rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
|
|
rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
|
|
|
|
/* enable phy interrupt */
|
|
HAL_ETH_WritePHYRegister(&EthHandle, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK);
|
|
#if defined(PHY_INTERRUPT_CTRL_REG)
|
|
HAL_ETH_WritePHYRegister(&EthHandle, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN);
|
|
#endif
|
|
#else /* PHY_USING_INTERRUPT_MODE */
|
|
stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,
|
|
NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
|
|
if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK)
|
|
{
|
|
LOG_E("Start link change detection timer failed");
|
|
}
|
|
#endif /* PHY_USING_INTERRUPT_MODE */
|
|
}
|
|
|
|
/* Register the EMAC device */
|
|
int rt_hw_stm32_eth_init(void)
|
|
{
|
|
rt_err_t state = RT_EOK;
|
|
|
|
/* Prepare receive and send buffers */
|
|
Rx_Buff = (rt_uint8_t *)rt_calloc(ETH_RXBUFNB, ETH_MAX_PACKET_SIZE);
|
|
if (Rx_Buff == RT_NULL)
|
|
{
|
|
LOG_E("No memory");
|
|
state = -RT_ENOMEM;
|
|
goto __exit;
|
|
}
|
|
|
|
Tx_Buff = (rt_uint8_t *)rt_calloc(ETH_TXBUFNB, ETH_MAX_PACKET_SIZE);
|
|
if (Tx_Buff == RT_NULL)
|
|
{
|
|
LOG_E("No memory");
|
|
state = -RT_ENOMEM;
|
|
goto __exit;
|
|
}
|
|
|
|
DMARxDscrTab = (ETH_DMADescTypeDef *)rt_calloc(ETH_RXBUFNB, sizeof(ETH_DMADescTypeDef));
|
|
if (DMARxDscrTab == RT_NULL)
|
|
{
|
|
LOG_E("No memory");
|
|
state = -RT_ENOMEM;
|
|
goto __exit;
|
|
}
|
|
|
|
DMATxDscrTab = (ETH_DMADescTypeDef *)rt_calloc(ETH_TXBUFNB, sizeof(ETH_DMADescTypeDef));
|
|
if (DMATxDscrTab == RT_NULL)
|
|
{
|
|
LOG_E("No memory");
|
|
state = -RT_ENOMEM;
|
|
goto __exit;
|
|
}
|
|
|
|
stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
|
|
stm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
|
|
|
|
/* OUI 00-80-E1 STMICROELECTRONICS. */
|
|
stm32_eth_device.dev_addr[0] = 0x00;
|
|
stm32_eth_device.dev_addr[1] = 0x80;
|
|
stm32_eth_device.dev_addr[2] = 0xE1;
|
|
/* generate MAC addr from 96bit unique ID (only for test). */
|
|
stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4);
|
|
stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2);
|
|
stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0);
|
|
|
|
stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
|
|
stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
|
|
stm32_eth_device.parent.parent.close = rt_stm32_eth_close;
|
|
stm32_eth_device.parent.parent.read = rt_stm32_eth_read;
|
|
stm32_eth_device.parent.parent.write = rt_stm32_eth_write;
|
|
stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
|
|
stm32_eth_device.parent.parent.user_data = RT_NULL;
|
|
|
|
stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
|
|
stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
|
|
|
|
/* register eth device */
|
|
state = eth_device_init(&(stm32_eth_device.parent), "e0");
|
|
if (RT_EOK == state)
|
|
{
|
|
LOG_D("emac device init success");
|
|
}
|
|
else
|
|
{
|
|
LOG_E("emac device init faild: %d", state);
|
|
state = -RT_ERROR;
|
|
goto __exit;
|
|
}
|
|
|
|
/* start phy monitor */
|
|
rt_thread_t tid;
|
|
tid = rt_thread_create("phy",
|
|
phy_monitor_thread_entry,
|
|
RT_NULL,
|
|
1024,
|
|
RT_THREAD_PRIORITY_MAX - 2,
|
|
2);
|
|
if (tid != RT_NULL)
|
|
{
|
|
rt_thread_startup(tid);
|
|
// LOG_I("√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√");
|
|
}
|
|
else
|
|
{
|
|
// LOG_E("----------------------------------");
|
|
state = -RT_ERROR;
|
|
}
|
|
__exit:
|
|
if (state != RT_EOK)
|
|
{
|
|
if (Rx_Buff)
|
|
{
|
|
rt_free(Rx_Buff);
|
|
}
|
|
|
|
if (Tx_Buff)
|
|
{
|
|
rt_free(Tx_Buff);
|
|
}
|
|
|
|
if (DMARxDscrTab)
|
|
{
|
|
rt_free(DMARxDscrTab);
|
|
}
|
|
|
|
if (DMATxDscrTab)
|
|
{
|
|
rt_free(DMATxDscrTab);
|
|
}
|
|
}
|
|
|
|
return state;
|
|
}
|
|
|
|
/**
|
|
* 关闭网口，去初始化，释放内存
|
|
*/
|
|
void rt_hw_stm32_eth_deinit()
|
|
{
|
|
// HAL_ETH_DeInit(&EthHandle);
|
|
rt_timer_delete(stm32_eth_device.poll_link_timer);
|
|
eth_device_deinit(&(stm32_eth_device.parent));
|
|
rt_pin_write(ETH_RESET_PIN, PIN_LOW);
|
|
if (Rx_Buff)
|
|
{
|
|
|
|
rt_free(Rx_Buff);
|
|
}
|
|
|
|
if (Tx_Buff)
|
|
{
|
|
rt_free(Tx_Buff);
|
|
}
|
|
|
|
if (DMARxDscrTab)
|
|
{
|
|
rt_free(DMARxDscrTab);
|
|
}
|
|
|
|
if (DMATxDscrTab)
|
|
{
|
|
rt_free(DMATxDscrTab);
|
|
}
|
|
HAL_ETH_DeInit(&EthHandle);
|
|
__HAL_RCC_ETH_CLK_DISABLE() ;
|
|
}
|
|
//MSH_CMD_EXPORT(rt_hw_stm32_eth_deinit, 去初始化网络。);
|
|
void setLinkUp()
|
|
{
|
|
/* send link up. */
|
|
eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
|
|
}
|
|
|
|
//INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);
|
|
//MSH_CMD_EXPORT(rt_hw_stm32_eth_init, 初始化网络。);
|
|
#endif
|
|
|