diff --git a/.config b/.config
index 8dda168..4b2d048 100644
--- a/.config
+++ b/.config
@@ -59,12 +59,15 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
 #
 # Memory Management
 #
-CONFIG_RT_USING_MEMPOOL=y
-CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_MEMPOOL is not set
+# CONFIG_RT_USING_SMALL_MEM is not set
 # CONFIG_RT_USING_SLAB is not set
-# CONFIG_RT_USING_MEMHEAP is not set
-CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
-# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BSET_MODE is not set
+# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
+CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
+CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
 # CONFIG_RT_USING_SLAB_AS_HEAP is not set
 # CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_NOHEAP is not set
diff --git a/applications/usrcfg.h b/applications/usrcfg.h
index adbd19d..f68742f 100644
--- a/applications/usrcfg.h
+++ b/applications/usrcfg.h
@@ -12,6 +12,15 @@
 
 #include "cfg.h"
 
+/* parameters for sram peripheral */
+/* stm32f4 Bank3:0X68000000 */
+#define SRAM_BANK_ADDR       ((uint32_t)0X68000000)
+
+/* data width: 8, 16, 32 */
+#define SRAM_DATA_WIDTH      16
+/* sram size */
+#define SRAM_SIZE            ((uint32_t)0x00100000)
+
 #define MIN_FRAME_LEN 10
 #define BUFFER_ROW 10//存储编码后信息的二维数组的维数
 
diff --git a/applications/w25q.c b/applications/w25q.c
index 0a20ce5..a1dbafe 100644
--- a/applications/w25q.c
+++ b/applications/w25q.c
@@ -87,4 +87,81 @@ void bootinfo()
     add_val("bootCnt");
 }
 /* 导出到自动初始化 */
-INIT_COMPONENT_EXPORT(bootinfo);
+INIT_APP_EXPORT(bootinfo);
+
+void sram_init(void)
+{
+    MX_FSMC_Init();
+}
+/* 导出到自动初始化 */
+INIT_COMPONENT_EXPORT(sram_init);
+
+
+static int sram_test(void)
+{
+    int i = 0;
+    uint32_t start_time = 0, time_cast = 0;
+#if SRAM_DATA_WIDTH == 8
+    char data_width = 1;
+    uint8_t data = 0;
+#elif SRAM_DATA_WIDTH == 16
+    char data_width = 2;
+    uint16_t data = 0;
+#else
+    char data_width = 4;
+    uint32_t data = 0;
+#endif
+
+    /* write data */
+    LOG_D("Writing the %ld bytes data, waiting....", SRAM_SIZE);
+    start_time = rt_tick_get();
+    for (i = 0; i < SRAM_SIZE / data_width; i++)
+    {
+#if SRAM_DATA_WIDTH == 8
+        *(__IO uint8_t *)(SRAM_BANK_ADDR + i * data_width) = (uint8_t)0x55;
+#elif SRAM_DATA_WIDTH == 16
+        *(__IO uint16_t *)(SRAM_BANK_ADDR + i * data_width) = (uint16_t)0x5555;
+#else
+        *(__IO uint32_t *)(SRAM_BANK_ADDR + i * data_width) = (uint32_t)0x55555555;
+#endif
+    }
+    time_cast = rt_tick_get() - start_time;
+    LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
+          time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
+
+    /* read data */
+    LOG_D("start Reading and verifying data, waiting....");
+    for (i = 0; i < SRAM_SIZE / data_width; i++)
+    {
+#if SRAM_DATA_WIDTH == 8
+        data = *(__IO uint8_t *)(SRAM_BANK_ADDR + i * data_width);
+        if (data != 0x55)
+        {
+            LOG_E("SRAM test failed!");
+            break;
+        }
+#elif SRAM_DATA_WIDTH == 16
+        data = *(__IO uint16_t *)(SRAM_BANK_ADDR + i * data_width);
+        if (data != 0x5555)
+        {
+            LOG_E("SRAM test failed!");
+            break;
+        }
+#else
+        data = *(__IO uint32_t *)(SRAM_BANK_ADDR + i * data_width);
+        if (data != 0x55555555)
+        {
+            LOG_E("SRAM test failed!");
+            break;
+        }
+#endif
+    }
+
+    if (i >= SRAM_SIZE / data_width)
+    {
+        LOG_D("SRAM test success!");
+    }
+
+    return RT_EOK;
+}
+MSH_CMD_EXPORT(sram_test, sram test);
diff --git a/drivers/board.c b/drivers/board.c
index 4572d60..9558371 100644
--- a/drivers/board.c
+++ b/drivers/board.c
@@ -228,3 +228,177 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
   }
 
 }
+
+
+
+static uint32_t FSMC_Initialized = 0;
+
+void HAL_FSMC_MspInit(void){
+    /* USER CODE BEGIN FSMC_MspInit 0 */
+
+    /* USER CODE END FSMC_MspInit 0 */
+    GPIO_InitTypeDef GPIO_InitStruct ={0};
+    if (FSMC_Initialized) {
+      return;
+    }
+    FSMC_Initialized = 1;
+
+    /* Peripheral clock enable */
+    __HAL_RCC_FSMC_CLK_ENABLE();
+
+    /** FSMC GPIO Configuration
+    PF0   ------> FSMC_A0
+    PF1   ------> FSMC_A1
+    PF2   ------> FSMC_A2
+    PF3   ------> FSMC_A3
+    PF4   ------> FSMC_A4
+    PF5   ------> FSMC_A5
+    PF12   ------> FSMC_A6
+    PF13   ------> FSMC_A7
+    PF14   ------> FSMC_A8
+    PF15   ------> FSMC_A9
+    PG0   ------> FSMC_A10
+    PG1   ------> FSMC_A11
+    PE7   ------> FSMC_D4
+    PE8   ------> FSMC_D5
+    PE9   ------> FSMC_D6
+    PE10   ------> FSMC_D7
+    PE11   ------> FSMC_D8
+    PE12   ------> FSMC_D9
+    PE13   ------> FSMC_D10
+    PE14   ------> FSMC_D11
+    PE15   ------> FSMC_D12
+    PD8   ------> FSMC_D13
+    PD9   ------> FSMC_D14
+    PD10   ------> FSMC_D15
+    PD11   ------> FSMC_A16
+    PD12   ------> FSMC_A17
+    PD13   ------> FSMC_A18
+    PD14   ------> FSMC_D0
+    PD15   ------> FSMC_D1
+    PG2   ------> FSMC_A12
+    PG3   ------> FSMC_A13
+    PG4   ------> FSMC_A14
+    PG5   ------> FSMC_A15
+    PD0   ------> FSMC_D2
+    PD1   ------> FSMC_D3
+    PD4   ------> FSMC_NOE
+    PD5   ------> FSMC_NWE
+    PG10   ------> FSMC_NE3
+    PE0   ------> FSMC_NBL0
+    PE1   ------> FSMC_NBL1
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+                            |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13
+                            |GPIO_PIN_14|GPIO_PIN_15;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
+    HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+                            |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
+                            |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
+                            |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
+                            |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15
+                            |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    /* USER CODE BEGIN FSMC_MspInit 1 */
+
+    /* USER CODE END FSMC_MspInit 1 */
+}
+
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){
+  /* USER CODE BEGIN SRAM_MspInit 0 */
+
+  /* USER CODE END SRAM_MspInit 0 */
+  HAL_FSMC_MspInit();
+  /* USER CODE BEGIN SRAM_MspInit 1 */
+
+  /* USER CODE END SRAM_MspInit 1 */
+}
+
+
+SRAM_HandleTypeDef hsram1;
+/* FSMC initialization function */
+void MX_FSMC_Init(void)
+{
+
+  /* USER CODE BEGIN FSMC_Init 0 */
+
+  /* USER CODE END FSMC_Init 0 */
+
+  FSMC_NORSRAM_TimingTypeDef Timing = {0};
+
+  /* USER CODE BEGIN FSMC_Init 1 */
+
+  /* USER CODE END FSMC_Init 1 */
+
+  /** Perform the SRAM1 memory initialization sequence
+  */
+  hsram1.Instance = FSMC_NORSRAM_DEVICE;
+  hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
+  /* hsram1.Init */
+  hsram1.Init.NSBank = FSMC_NORSRAM_BANK3;
+  hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
+  hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
+  hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
+  hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
+  hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
+  hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
+  hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
+  hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
+  hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
+  hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
+  hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
+  hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
+  hsram1.Init.PageSize = FSMC_PAGE_SIZE_NONE;
+  /* Timing */
+  Timing.AddressSetupTime = 0;
+  Timing.AddressHoldTime = 0;
+  Timing.DataSetupTime = 8;
+  Timing.BusTurnAroundDuration = 0;
+  Timing.CLKDivision = 0;
+  Timing.DataLatency = 0;
+  Timing.AccessMode = FSMC_ACCESS_MODE_A;
+  /* ExtTiming */
+
+  if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
+  {
+      Error_Handler( );
+  }
+
+  /* USER CODE BEGIN FSMC_Init 2 */
+  else {
+//      LOG_I("sram init success, mapped at 0x%X, size is %d bytes, data width is %d", SRAM_BANK_ADDR, SRAM_SIZE, SRAM_DATA_WIDTH);
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+      /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
+
+      static struct rt_memheap sram_heap;
+      rt_memheap_init(&sram_heap, "sram", (void *)SRAM_BANK_ADDR, SRAM_SIZE);
+#endif
+  }
+  /* USER CODE END FSMC_Init 2 */
+}
+
+
diff --git a/drivers/board.h b/drivers/board.h
index 1706b28..d9cf8c0 100644
--- a/drivers/board.h
+++ b/drivers/board.h
@@ -401,6 +401,7 @@ extern "C"
 ////#define RESET_LB GET_PIN(E, 1)
 ////#define RESET_UB GET_PIN(E, 0)
 ////#define RESET_CE GET_PIN(G, 10)
+#define HAL_SRAM_MODULE_ENABLED
 /*-------------------------- ON_CHIP_FLASH CONFIG END --------------------------*/
 
 #ifdef __cplusplus
diff --git a/rtconfig.h b/rtconfig.h
index 601535a..72e8737 100644
--- a/rtconfig.h
+++ b/rtconfig.h
@@ -38,9 +38,10 @@
 
 /* Memory Management */
 
-#define RT_USING_MEMPOOL
-#define RT_USING_SMALL_MEM
-#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_MEMHEAP_AS_HEAP
+#define RT_USING_MEMHEAP_AUTO_BINDING
 #define RT_USING_HEAP
 /* end of Memory Management */
 
@@ -303,7 +304,7 @@
 #define SYSWATCH_EXCEPT_CONFIRM_TMO 15
 #define SYSWATCH_EXCEPT_RESUME_DLY 15
 #define SYSWATCH_THREAD_PRIO 0
-#define SYSWATCH_THREAD_STK_SIZE 1024*2
+#define SYSWATCH_THREAD_STK_SIZE 1024
 #define SYSWATCH_THREAD_NAME "syswatch"
 #define SYSWATCH_WDT_NAME "wdt"
 #define SYSWATCH_WDT_TIMEOUT 5
@@ -389,5 +390,5 @@
 
 /* end of samples: kernel and components samples */
 #define RT_STUDIO_BUILT_IN
-
+#define HAL_SRAM_MODULE_ENABLED
 #endif